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ltm4628 1 4628fd typical a pplica t ion descrip t ion dual 8a or single 16a dc/dc module regulator the lt m ? 4628 is a complete dual 8 a output switching mode dc/dc power supply and can be easily configured to provide a single 2- phase 16 a output. included in the package are the switching controller, power fets, inductor , and all supporting components. operating from an input voltage range of 4.5 v to 26.5 v, the ltm4628 supports two outputs each with an output voltage range of 0.6 v to 5.5v, set by a single external resistor. its high efficiency design delivers 8 a continuous current for each output. only a few input and output capacitors are needed. the device supports frequency synchronization, multi- phase operation, burst mode operation and output voltage tracking for supply rail sequencing. it has an onboard temperature diode for device temperature monitoring. high switching frequency and a current mode architec- ture enable a very fast transient response to line and load changes without sacrificing stability. fault protection features include overvoltage and over- current protection. the power module is offered in space saving and thermally enhanced 15 mm 15 mm 4.32mm lga and 15 mm 15 mm 4.92 mm bga packages. the ltm4628 is rohs compliant with pb-free finish. l, lt , lt c , lt m , linear technology, the linear logo, module, burst mode and polyphase are registered and l tpowercad is a trademarks of linear technology corporation. all other trademarks are the property of their respective owners. dual 8a, 1.5v and 1.2v output dc/dc module ? regulator fea t ures a pplica t ions n complete standalone dual power supply n single 16a or dual 8a output n wide input voltage range: 4.5v to 26.5v n output voltage range: 0.6v to 5.5v n 1.5% total dc output error n differential remote sense amplifier n current mode control/fast transient response n adjustable switching frequency n overcurrent foldback protection n multiphase parallel current sharing with multiple ltm4628s n frequency synchronization n internal temperature sensing diode output n selectable burst mode ? operation n soft-start/voltage tracking n output overvoltage protection n small surface mount footprint, low profile 15mm 15mm 4.32mm lga and 15mm 15mm 4.92mm bga packages n telecom and networking equipment n storage and atca cards n industrial equipment efficiency and power loss at 12v input 4628 ta01a ltm4628 v in temp run1 run2 track1 track2 f set 470f 6.3v 40.2k 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 v out2 1.2v at 8a v out1 1.5v at 8a sw2 pgood2 mode_pllin clkout intv cc extv cc pgood1 sgnd gnd diffp diffn diffout 60.4k 470f 6.3v 100f 6.3v 100k 10k 5.1v zener * * * pull-up resistor and zener are optional. v in 4.5v to 26.5v 120k 0.1f 10f 35v 4 4.7f load current (a) 0 efficiency (%) power loss (w) 95 90 80 85 75 70 65 60 55 50 2.0 1.8 1.4 1.2 1.6 1.0 0 0.2 0.4 0.6 0.8 4 2 4628 ta01b 8 3 1 5 6 7 power loss efficiency 1.2v 1.5v
ltm4628 2 4628fd p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in ............................................................. C 0.3 v to 28 v v sw 1 , v sw 2 .................................................... C1 v to 28 v pgood 1, pgood2, run 1, run 2, intv cc , extv cc ........................................... C 0.3 v to 6v mode _ pllin , f set , track 1, track 2, diffout , phasmd ............................... C 0. 3 v to intv cc v out 1 , v out 2 , v outs 1 , v outs 2 ..................... C 0.3 v to 6v (note 1) lga package 144-lead (15mm 15mm 4.32mm) top view temp comp2 v in 1 2 3 4 5 6 7 v fb1 v fb2 sgnd 8 109 11 12 l k j h sw1 clkout phasmd mode_pllin run1 gnd gnd sw2 track2 diffp diffn g f e d c b m a v out1 v out2 v outs1 v outs2 sgnd gnd track1 comp1 diffout run2 pgood1 pgood2 f set sgnd extv cc intv cc t jmax = 125c, jctop = 17c/w, jcbottom = 2.75c/w, jb + ba = 11c/w, ja = 9.5c/wC11c/w, ba = board to ambient resistance, values defined per jesd 51-12 weight = 2.7g bga package 144-lead (15mm 15mm 4.92mm) top view temp comp2 v in 1 2 3 4 5 6 7 v fb1 v fb2 sgnd 8 109 11 12 l k j h sw1 clkout phasmd mode_pllin run1 gnd gnd sw2 track2 diffp diffn g f e d c b m a v out1 v out2 v outs1 v outs2 sgnd gnd track1 comp1 diffout run2 pgood1 pgood2 f set sgnd extv cc intv cc t jmax = 125c, jctop = 17c/w, jcbottom = 2.75c/w, jb + ba = 11c/w, ja = 9.5c/wC11c/w, ba = board to ambient resistance, values defined per jesd 51-12 weight = 2.9g lead free finish tray part marking* package description temperature range ? ltm4628ev#pbf ltm4628ev#pbf ltm4628v 144-lead (15mm 15mm 4.32mm) lga C40c to 125c ltm4628iv#pbf ltm4628iv#pbf ltm4628v 144-lead (15mm 15mm 4.32mm) lga C40c to 125c ltm4628ey#pbf ltm4628ey#pbf ltm4628y 144-lead (15mm 15mm 4.92mm) bga C40c to 125c ltm4628iy#pbf ltm4628iy#pbf ltm4628y 144-lead (15mm 15mm 4.92mm) bga C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. ? see note 2. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ o r d er i n f or m a t ion diffp , diffn ......................................... C 0.3 v to intv cc v fb 1 , v fb 2 , comp 1, comp 2 ( note 6) ........ C 0. 3 v to 2.7 v intv cc peak output current ................................ 10 0 ma internal operating temperature range ( note 2) .................................................. C 4 0 c to 125 c storage temperature range .................. C 5 5 c to 125 c peak package body temperature .......................... 24 5 c
ltm4628 3 4628fd e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range (note 2). specified as each individual output channel. t a = 25c, v in = 12v and v run1 , v run2 at 5v unless otherwise noted, per the typical application in figure 28. symbol parameter conditions min typ max units v in input dc voltage l 4.5 26.5 v v out output voltage l 0.6 5.5 v v out1(dc) , v out2(dc) output voltage, total variation with line and load c in = 22f 3, c out = 100f 1 ceramic, 470f poscap, mode_pllin = gnd, rfb1, rfb2 = 40.2k, v in = 4.5v to 26.5v, i out = 0a to 8a l 1.477 1.5 1.523 v input specifications v run1 , v run2 run pin on/off threshold run rising 1.1 1.25 1.40 v v run1hys , v run2hys run pin on hysteresis 150 mv i inrush(vin) input inrush current at start-up i out = 0a, c in = 22f 3, c out = 100f , 470f poscap v out1 = 1.5v, v out2 = 1.5v, v in = 12v, track = 0.01f 1 a i q(vin) input supply bias current v in = 12v, v out = 1.5v, burst mode operation v in = 12v, v out = 1.5v, pulse-skipping mode v in = 12v, v out = 1.5v, switching continuous shutdown, run = 0, v in = 12v 5 15 65 60 ma ma ma a i s(vin) input supply current v in = 4.75v, v out = 1.5v, i out = 8a v in = 12v, v out = 1.5v, i out = 8a v in = 26.5v, v out = 1.5v, i out = 8a 2.9 1.18 0.575 a a a output specifications i out1(dc) , i out2(dc) output continuous current range v in = 12v, v out = 1.5v (note 7) 0 8 a v out1(line) /v out1 v out2(line) /v out2 line regulation accuracy v out = 1.5v, v in from 4.5v to 26.5v i out = 0a for each output, l 0.010 0.04 %/v v out1(load) /v out1 v out2(load) /v out2 load regulation accuracy for each output, v out = 1.5v, 0a to 8a v in = 12v (note 7) l 0.15 0.3 % v out1(ac) , v out2(ac) output ripple voltage i out = 0a, c out = 100f x5r ceramic, 470f poscap v in = 12v, v out = 1.5v 15 mv p-p f s (each channel) output ripple voltage frequency v in = 12v, v out = 1.5v, f set = 2.5v (note 4) 780 khz f sync (each channel) sync capture range 400 780 khz v outstart (each channel) turn-on overshoot c out = 100f x5r ceramic, 470f poscap, v out = 1.5v, i out = 0a v in = 12v 10 mv t start (each channel) turn-on time c out = 100f x5r ceramic, 470f poscap, no load, track/ss with 0.01f to gnd, v in = 12v 5 ms v out(ls) (each channel) peak deviation for dynamic load load: 0% to 50% to 0% of full load c out = 22f 3 x5r ceramic, 470f poscap v in = 12v, v out = 1.5v 30 mv t settle (each channel) settling time for dynamic load step load: 0% to 50% to 0% of full load, v in = 12v, c out = 100f, c out = 470f 20 s i out(pk) (each channel) output current limit v in = 12v, v out = 1.5v 15 a control section v fb1 , v fb2 voltage at v fb pins i out = 0a, v out = 1.5v l 0.592 0.600 0.606 v i fb1 , i fb2 leakage current of v fb1 , v fb2 (note 6) C5 C20 na v ovl feedback overvoltage lockout l 0.64 0.66 0.68 v
ltm4628 4 4628fd e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range (note 2). specified as each individual output channel. t a = 25c, v in = 12v and vrun1, vrun2 at 5v unless otherwise noted, per the typical application in figure 28. symbol parameter conditions min typ max units i track1 , i track2 track pin soft-start pull-up current track1, track2 = 0v 1 1.25 1.5 a uvlo undervoltage lockout threshold v in falling v in rising 3.3 3.9 v v uvlo hysteresis 0.6 v t on(min) minimum on-time (note 6) 90 ns r fbhi1 , r fbhi2 resistor between v outs1 , v outs2 and v fb1 , v fb2 pins for each output 60.05 60.4 60.75 k? v ol_pgood (each channel) pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 5 a v pgood pgood trip level v fb with respect to set output voltage v fb ramping negative v fb ramping positive C10 10 % % intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 26.5v 4.8 5 5.2 v v intvcc load regulation intv cc load regulation i cc = 0ma to 50ma 0.5 2 % v extvcc extv cc switchover voltage extv cc ramping positive 4.5 4.7 v v extvcc(drop) extv cc dropout i cc = 20ma, v extvcc = 5v 50 100 mv v extvcc(hyst) extv cc hysteresis 200 mv oscillator and phase-locked loop f nom nominal frequency f set = 1.2v 450 500 550 khz f low lowest frequency f set = 0v (note 5) 210 250 290 khz f high highest frequency f set > 2.4v, up to intv cc 700 780 860 khz i fset frequency set current 9 10 11 a r mode_pllin mode_pllin input resistance 250 k ph clkout phase (relative to v out1 ) phasmd = gnd phasmd = float phasmd = int v cc 60 90 120 deg deg deg v oh_clkout v ol_clkout clock high output voltage clock low output voltage 2 0.2 v v differential amplifier a v voltage gain 1 v/v r in input resistance measured at diffp input 80 k? v os input offset voltage v diffp = v diffout = 1.5v, i diffout = 100a 3 mv psrr power supply rejection ratio 5v < v in < 20v 90 db i cl maximum output current 3 ma diffout (max) maximum output voltage i diffout = 300a intv cc C 1.4v v gbw gain bandwidth product 3 mhz
ltm4628 5 4628fd note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4628 is tested under pulsed load conditions such that t j t a . the ltm4628e is guaranteed to meet specifications from 0c to 125c internal temperature. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4628i is guaranteed over the full C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: tw o outputs are tested separately and the same testing condition is applied to each output. note 4: the switching frequency is programmable for 400khz to 750khz. note 5: ltm4628 device is designed to operate from 400khz to 750khz note 6: 100% tested at wafer level. note 7: see output current derating curves for different v in , v out and t a . typical p er f or m ance c harac t eris t ics burst mode pulse-skipping efficiency 0.8v load transient 1.2v load transient 5v in efficiency 12v in efficiency 24v in efficiency output current (a) 0 efficiency (%) 90 95 8 4628 g01 85 80 65 70 2 4 6 1 3 5 7 75 100 3.3v out 2.5v out 1.5v out 1.2v out 0.8v out freq = 500khz output current (a) 0 efficiency (%) 90 95 8 4628 g02 85 80 55 70 2 4 6 1 3 5 7 75 60 65 100 5v out 3.3v out 2.5v out 1.5v out 1.2v out 0.8v out freq = 500khz, 700khz for 3.3v and 5v output current (a) 0 efficiency (%) 85 90 8 4628 g03 80 75 50 65 2 4 6 1 3 5 7 70 55 60 95 5v out 3.3v out 2.5v out 1.5v out freq = 500khz, 700khz for 3.3v and 5v 12v in , 0.8v out , 0a to 4a load step at 4a/s c out1 4 100f 6.3v x5r ceramic 1210 case size switching frequency 400khz c ff capacitor = 47pf 4628 g05 100s/div v out 50mv/div i out 2a/div 12v in , 1.2v out , 0a to 4a load step at 4a/s c out1 , 4 100f 6.3v x5r ceramic 1210 case size switching frequency 500khz c ff capacitor = 47pf 4628 g06 v out 50mv/div i out 2a/div 100s/div output current (a) 0.001 efficiency (%) 70 80 90 10 1 4628 g04 60 50 0 30 0.1 0.01 40 10 20 100 pulse-skipping mode burst mode operation e lec t rical c harac t eris t ics
ltm4628 6 4628fd typical p er f or m ance c harac t eris t ics output short-circuit output short-circuit coincident tracking 3.3v load transient output start-up output start-up 12v in , 3.3v out , 0a to 4a load step at 4a/s c out1 , 4 100f 6.3v x5r ceramic 1210 case size switching frequency 500khz c ff capacitor = 47pf 4628 g10 v out 100mv/div i out 2a/div 100s/div 4628 g11 v out 1v/div 5ms/div input current 1a/div 20ms/div v in = 12v v out = 2.5v i out = 0a 4628 g12 v out 1v/div 5ms/div input current 1a/div 20ms/div v in = 12v v out = 2.5v i out = 8a 4628 g13 v out 1v/div 5ms/div input current 2a/div 50s/div v in = 12v v out = 2.5v i out = 0a 4628 g14 v out 1v/div 5ms/div input current 2a/div 50s/div v in = 12v v out = 2.5v i out = 8a 4628 g15 10ms/div v out1 = 1.8v at 8a v out2 = 1.2v at 8a 1.5v load transient 1.8v load transient 2.5v load transient 12v in , 1.5v out , 0a to 4a load step at 4a/s c out1 4 100f 6.3v x5r ceramic 1210 case size switching frequency 500khz c ff capacitor = 47pf 4628 g07 v out 50mv/div i out 2a/div 100s/div 12v in , 1.8v out , 0a to 4a load step at 4a/s c out1 4 100f 6.3v x5r ceramic 1210 case size switching frequency 500khz c ff capacitor = 47pf 4628 g08 v out 50mv/div i out 2a/div 100s/div 12v in , 2.5v out , 0a to 4a load step at 4a/s c out1 , 4 100f 6.3v x5r ceramic 1210 case size switching frequency 500khz c ff capacitor = 47pf 4628 g09 v out 100mv/div i out 2a/div 100s/div
ltm4628 7 4628fd p in func t ions v out1 ( a1-a5, b1-b5, c1-c4): power output pins. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. review table 4. gnd ( a6-a7, b6-b7, d1-d4, d9-d12, e1-e4, e10-e12, f1-f3, f10-f12, g1, g3, g10, g12, h1-h7, h9-h12, j1, j5, j8, j12, k1, k5-k8, k12, l1, l12, m 1 , m12): power ground pins for both input and output returns. v out2 ( a8-a12, b8-b12, c9-c12): power output pins. apply output load between these pins and gnd pins. rec- ommend placing output decoupling capacitance directly between these pins and gnd pins. review table 4. v outs1 , v outs2 ( c5, c8): this pin is connected to the top of the internal top feedback resistor for each output. the pin can be directly connected to its specific output, or connected to diffout when the remote sense amplifier is used. in paralleling modules, one of the v outs pins is connected to the diffout pin in remote sensing or directly to v out with no remote sensing. it is very important to connect these pins to either the diffout or v out since this is the feedback path, and cannot be left open. see the applications information section. f set (c6): frequency set pin. a 10 a current is sourced from this pin. a resistor from this pin to ground sets a voltage that in turn programs the operating frequency. alternatively, this pin can be driven with a dc voltage that can set the operating frequency. see the applications information section. sgnd ( c7, d6, g6-g7, f6-f7): signal ground pin. return ground path for all analog and low power circuitry. tie a single connection to the output capacitor gnd in the ap- plication. see layout guidelines in figure 27. v fb1 , v fb2 ( d5, d7): the negative input of the error amplifier for each channel. internally, this pin is con- nected to v outs1 or v outs2 with a 60.4 k? precision resistor. different output voltages can be programmed with an additional resistor between v fb and gnd pins. in polyphase ? operation, tying the v fb pins together allows for parallel operation. see the applications information section for details. (recommended to use test points to monitor signal pin connections.) comp1 and comp2 vs output current i out1 and i out2 vs total current for parallel operation total output current (a) 0 i out1 and i out2 (a) 7 8 16 4628 g16 6 5 0 3 4 8 12 2 6 10 14 4 1 2 9 i out1 i out2 output current (a) 0 comp (v) 1.2 1.3 9 4628 g17 1.1 1.0 0.5 0.8 2 4 6 8 1 3 5 7 0.9 0.6 0.7 1.4 v ith1 v ith2 typical p er f or m ance c harac t eris t ics
ltm4628 8 4628fd p in func t ions track1, track 2 ( e5, d8): output voltage tracking pin and soft-start inputs. each channel has a 1.3 a pull-up current source. when one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. the remaining channel can be set up as the slave, and have the masters output applied through a voltage divider to the slave out- puts track pin. this voltage divider is equal to the slave outputs feedback divider for coincidental tracking. see the applications information section. comp1, comp 2 ( e6, e7): current control threshold and error amplifier compensation point for each channel. the current comparator threshold increases with this control voltage. tie the comp pins together for parallel operation. the device is internal compensated. diffp (e8): positive input of the remote sense amplifier. this pin is connected to the remote sense point of the output voltage. use of the remote sense amplifier is limited to an output voltage between 0.6 v and 3.3 v inclusive. connect to gnd if not used. see the applications information section. diffn (e9): negative input of the remote sense amplifier. this pin is connected to the remote sense point of the output gnd. see the applications information section. mode_pllin (f4): force continuous mode, burst mode operation, or pulse-skipping mode selection pin and external synchronization input to phase detector pin. connect this pin to sgnd to force both channels into force continuous mode of operation. connect to intv cc to enable pulse-skipping mode of operation. leaving the pin floating will enable burst mode operation. a clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. run1, run 2 ( f5, f9): run control pin. a voltage above 1.25v will turn on each channel in the module. a voltage below 1.25 v on the run pin will turn off the related chan- nel. each run pin has a 1 a pull-up current, once the run pin reaches 1.2 v an additional 4.5 a pull-up current is added to this pin. diffout (f8): internal remote sense amplifier output. connect this pin to v outs1 or v outs2 depending on which output is using remote sense. in parallel operation con- nect one of the v outs pin to diffout for remote sensing. leave floating if the remote sense amplifier is not used. sw 1, sw2 ( g2, g11): switching node of each channel that is used for testing purposes. also an r-c snubber network can be applied to reduce or eliminate switch node ringing, otherwise leave floating. see the applications information section. phasmd (g4): connect this pin to sgnd, intv cc , or float- ing this pin to select the phase of clkout to 60 degrees, 120 degrees, and 90 degrees respectively. clkout (g5): clock output with phase control using the phasmd pin to enable multiphase operation between devices. see the applications information section. pgood1, pgood 2 (g 9, g 8): output voltage power good indicator. open drain logic output that is pulled to ground when the output voltage is not within 7.5% of the regulation point. intv cc (h8): internal 5 v regulator output. the control circuits and internal gate drivers are powered from this voltage. intv cc is controlled and enabled when run1 or run2 is activated high. decouple this pin to pgnd with a 4.7f low esr tantalum or ceramic. temp (j6): onboard temperature diode for monitoring the vbe junction voltage change with temperature. see the applications information section. extv cc (j7): external power input that is enabled through a switch to intv cc whenever extv cc is greater than 4.7 v. do not exceed 6 v on this input, and connect this pin to v in when operating v in on 5 v. an efficiency increase will occur that is a function of the (v in C intv cc ) multiplied by power mosfet driver current. typical current requirement is 30 ma. v in must be applied before extv cc , and extv cc must be removed before v in . v in ( m2-m11, l2-l11, j2-j4, j9-j11, k2-k4, k9-k11): power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. (recommended to use test points to monitor signal pin connections.)
ltm4628 9 4628fd s i m pli f ie d b lock diagra m 4628 bd temp clkout run1 mode_pllin phasemd track1 4.7f ss cap 1f c in1 10f 35v v in v in c in2 10f 35v r fb2 60.4k mtop1 mbot1 power control 2.2f 0.68h 60.4k c out1 r fb1 40.2k + 1.5v/8a 1.2v/8a v fb1 gnd gnd gnd gnd sw2 sw1 pgood2 pgood1 internal comp internal comp internal filter 1f c in3 10f 35v mtop2 mbot2 c in4 10f 35v 2.2f 0.68h c out2 + + ? 60.4k xi v out1 v out2 v fb2 v outs2 v outs1 r fset v in r t ss cap diffout diffn diffp comp1 sgnd track2 intv cc extv cc run2 comp2 f set sgnd v in r t 100a = decoupling r equire m en t s symbol parameter conditions min typ max units c in1 , c in3 c in2 , c in4 external input capacitor requirement (v in1 = 4.5v to 26.5v, v out1 = 1.5v) (v in2 = 4.5v to 26.5v, v out2 = 1.5v) i out1 = 8a i out2 = 8a 22 22 f f c out1 c out2 external output capacitor requirement (v in1 = 4.5v to 26.5v, v out1 = 1.5v) (v in2 = 4.5v to 26.5v, v out2 = 1.5v) i out1 = 8a i out2 = 8a 300 300 f f t a = 25c. use figure 1 configuration. figure 1. simplified ltm4628 block diagram
ltm4628 10 4628fd o pera t ion power module description the ltm4628 is a dual-output standalone nonisolated switching mode dc/dc power supply. it can provide two 8a outputs with few external input and output capacitors and setup components. this module provides precisely regulated output voltages programmable via external resistors from 0.6v dc to 5v dc over 4.5 v to 26.5 v input voltages. the typical application schematic is shown in figure 28. the ltm4628 has dual integrated constant-frequency cur- rent mode regulators and built-in power mosfet devices with fast switching speed. the typical switching frequency is 550 khz. for switching-noise sensitive applications, it can be externally synchronized from 400 khz to 780khz. a resistor can be used to program a free run frequency on the f set pin. see the applications information section. with current mode control and internal feedback loop compensation, the ltm4628 module has sufficient stabil- ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. internal overvoltage and undervoltage comparators pull the open-drain pgood outputs low if the output feedback voltage exits a 7.5% window around the regulation point. if the output voltage exceeds 10% above its normal op- erating point then the bottom power mosfet will try to clamp the output to protect it. pulling the run pins below 1.1 v forces the regulators into a shutdown state, by turning off both mosfets. the track pins are used for programming the output voltage ramp and voltage tracking during start-up or used for soft-starting the regulator. see the applications information section. the ltm4628 is internally compensated to be stable over all operating conditions. table 2 provides a guideline for input and output capacitances for several operating conditions. ltpowercad? is available for transient and stability analysis. the v fb pin is used to program the output voltage with a single external resistor to ground. a differential remote sense amplifier is available for sens- ing the output voltage accurately on one of the outputs at the load point, or in parallel operation sensing the output voltage at the load point. multiphase operation can be easily employed with the mode_pllin, phasmd, and clkout pins. up to 12 phases can be cascaded to run simultaneously with re- spect to each other by programming the phasmd pin to different levels. see the applications information section. high efficiency at light loads can be accomplished with selectable burst mode operation or pulse- skipping operation using the mode_pllin pin. these light load features will accommodate battery operation. efficiency graphs are provided for light load operation in the typical performance characteristics section. see the applications information section for details. a temperature diode is included inside the module to moni- tor the temperature of the module. see the applications information section for details. the switch pins are available for functional operation monitoring and a resistor-capacitor snubber circuit can be carefully placed on the switch pin to ground to dampen any high frequency ringing on the transition edges. see the applications information section for details.
ltm4628 11 4628fd the typical ltm4628 application circuit is shown in figure 28. external component selection is primarily determined by the maximum load current and output voltage. refer to table 4 for specific external capacitor requirements for particular applications. v in to v out step-down ratios there are restrictions in the maximum v in and v out step- down ratio that can be achieved for a given input voltage. each output of the ltm4628 is capable of 98% duty cycle, but the v in to v out minimum dropout is still shown as a function of its load current and will limit output current capability related to high duty cycle on the top side switch. minimum on-time t on(min) is another consideration in operating at a specified duty cycle while operating at a certain frequency due to the fact that t on(min) < d/f sw , where d is duty cycle and f sw is the switching frequency. t on(min) is specified in the electrical parameters as 90ns. output voltage programming the pwm controller has an internal 0.6 v reference voltage. as shown in the block diagram, a 60.4 k? internal feedback resistor connects between the v outs1 to v fb1 and v outs2 to v fb2 . it is very important that these pins be connected to their respective outputs for proper feedback regulation. overvoltage can occur if these v outs1 and v outs2 pins are left floating when used as individual regulators, or at least one of them is used in paralleled regulators. the output voltage will default to 0.6 v with no feedback resistor on either v fb1 or v fb2 . adding a resistor r fb from v fb pin to gnd programs the output voltage: v out = 0.6v ? 60.4k + r fb r fb table 1. v fb resistor table vs various output voltages v out 0.6v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 5.0v r fb open 90.9k 60.4k 40.2k 30.2k 19.1k 13.3k 8.25k for parallel operation of multiple channels the same feed- back setting resistor can be used for the parallel design. this is done by connecting the v outs1 to the output as shown in figure 2, thus tying one of the internal 60.4k resistors to the output . all of the v fb pins tie together with one programming resistor as shown in figure 2. a pplica t ions i n f or m a t ion in parallel operation the v fb pins have an i fb current of 20na maximum each channel. to reduce output voltage error due to this current, an additional v outs pin can be tied to v out , and an additional r fb resistor can be used to lower the total thevenin equivalent resistance seen by this current. for example in figure 2, the total thevenin equivalent resistance of the v fb pin is (60.4k // r fb ), which is 30.2 k where r fb is equal to 60.4 k for a 1.2 v output. four phases connected in parallel equates to a worse case feedback current of 4?i fb equals 80na maximum. the volt- age error is 80na ? 30.2k = 2.4 mv. if v outs2 is connected as shown in figure 2 to v out , and another 60.4 k resistor is connected from v fb2 to ground, then the voltage error is reduced to 1.2 mv. if the voltage error is acceptable then no additional connections are necessary. the onboard 60.4k resistor is 0.5% accurate and the v fb resistor can be chosen by the user to be as accurate as needed. all comp pins are tied together for current sharing between the phases. the track pins can be tied together and a single soft- start capacitor can be used to soft- start the regula- tor. the soft- start equation will need to have the soft- start current parameter increased by the number of paralleled channels. see the output voltage tracking section. figure 2. 4-phase parallel configurations 4628 f02 60.4k track1 track2 v out1 v outs1 v fb1 v fb2 comp1 4 paralleled outputs for 1.2v at 32a optional connection comp2 v outs2 v out2 60.4k 60.4k track1 track2 0.1f v out1 v outs1 v fb1 v fb2 comp1 comp2 v outs2 v out2 60.4k ltm4628 ltm4628 r fb 60.4k optional r fb 60.4k used to lower total thevenin equivalent to lower i fb voltage error
ltm4628 12 4628fd a pplica t ions i n f or m a t ion input capacitors the ltm4628 module should be connected to a low ac- impedance dc source. for the regulator input three 22f, or four 10 f input ceramic capacitors are used for rms ripple current . a 47 f to 100 f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. this bulk input capacitor is only needed if the input source impedance is compromised by long in- ductive leads, traces or not enough source capacitance. if low impedance power planes are used, then this bulk capacitor is not needed. for a buck converter, the switching duty-cycle can be estimated as: d = v out v in without considering the inductor current ripple, for each output, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ? 1 ? d ( ) in the above equation, % is the estimated efficiency of the power module. the bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or a polymer capacitor. output capacitors the ltm4628 is designed for low output voltage ripple noise and good transient response. the bulk output capacitors defined as c out are chosen with low enough effective series resistance ( esr) to meet the output volt- age ripple and transient requirements. c out can be a low esr tantalum capacitor, the low esr polymer capacitor or ceramic capacitor. the typical output capacitance range for each output is from 200 f to 470 f. additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. table 4 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 4 a/s transient. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient performance. stability criteria are considered in the table 4 matrix, and ltpowercad? is available for stability analysis. multiphase operation will reduce effective output ripple as a function of the num- ber of phases. application note 77 discusses this noise reduction versus output ripple current cancellation , but the output capacitance should be considered carefully as a function of stability and transient response. ltpowercad can calculate the output ripple reduction as the number of implemented phases increases by n times. a small value 10? to 50 ? resistor can be placed in series from v out to the v outs pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. the same resistor could be placed in series from v out to diffp and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. burst mode operation the ltm4628 is capable of burst mode operation on each regulator in which the power mosfets operate intermittently based on load demand, thus saving quiescent current. for applications where maximizing the efficiency at very light loads is a high priority, burst mode operation should be applied. burst mode operation is enabled with the mode_pllin pin floating. during this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal opera- tion even though the voltage at the comp pin indicates a lower value . the voltage at the comp pin drops when the inductors average current is greater than the load requirement. as the comp voltage drops below 0.5 v, the burst comparator trips, causing the internal sleep line to go high and turn off both power mosfets. in sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450 a for each output. the load current is now being supplied from the output capacitors. when the output voltage drops, caus- ing comp to rise above 0.5 v, the internal sleep line goes low, and the ltm4628 resumes normal operation. the next oscillator cycle will turn on the top power mosfet and the switching cycle repeats. either regulator can be configured for burst mode operation.
ltm4628 13 4628fd a pplica t ions i n f or m a t ion pulse-skipping mode operation in applications where low output ripple and high efficiency at intermediate currents are desired, pulse - skipping mode should be used. pulse-skipping operation allows the ltm4628 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. tying the mode_pllin pin to intv cc enables pulse-skipping operation. at light loads the internal current comparator may remain tripped for several cycles and force the top mosfet to stay off for several cycles, thus skipping cycles. the inductor current does not reverse in this mode. this mode will maintain higher effective frequencies thus lower output ripple and lower noise than burst mode operation. either regulator can be configured for pulse- skipping mode. forced continuous operation in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode_pllin pin to sgnd. in this mode, inductor current is allowed to reverse during low output loads, the comp voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start - up , forced continuous mode is disabled and inductor current is prevented from reversing until the ltm4628s output voltage is in regulation. either regulator can be configured for forced continuous mode. multiphase operation for output loads that demand more than 8 a of current, two outputs in ltm4628 or even multiple ltm4628s can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripple. the mode_pllin pin allows the ltm4628 to synchronize to an external clock (between 400 khz and 780 khz) and the internal phase-locked loop allows the ltm4628 to lock figure 3. examples of 2-phase, 4-phase, and 6-phase operation with phasmd table 4628 f03 v out2 180 phase 0 phase mode_pllin v out1 phasmd clkout phasmd pin status and corresponding phase relationship sgnd or float 2-phase design 4-phase design 6-phase design 90 degree float v out2 180 phase 0 phase float mode_pllin v out1 phasmd clkout v out2 270 phase 90 phase float mode_pllin v out1 phasmd clkout 60 degree 60 degree v out2 180 phase 0 phase sgnd mode_pllin v out1 phasmd clkout v out2 240 phase 60 phase sgnd mode_pllin v out1 phasmd clkout v out2 300 phase 120 phase float mode_pllin v out1 phasmd clkout phasmd sgnd controller1 controller2 clkout float intv cc 0 0 0 180 180 240 60 90 120
ltm4628 14 4628fd onto incoming clock phase as well. the clkout signal can be connected to the mode_pllin pin of the following stage to line up both the frequency and the phase of the entire system. tying the phasmd pin to intv cc , sgnd, or left floating generates a phase difference (between mode_pllin and clkout) of 120 degrees, 60 degrees, or 90 degrees respectively. a total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the phasmd pin of each ltm4628 chan- nel to different levels. figure 3 shows a 2- phase design, 4-phase design and a 6- phase design example for clock phasing with the phasmd table. a multiphase power supply significantly reduces the amount of ripple current in both the input and output ca- pacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used ( assuming that the input voltage is greater a pplica t ions i n f or m a t ion than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. the ltm4628 device is an inherently current mode con- trolled device, so parallel modules will have very good current sharing. this will balance the thermals on the design. figure 31 shows an example of parallel operation and pin connection. input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current cancel- lation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases. figure 4 shows this graph. figure 4. input rms current ratios to dc load current as a function of duty cycle duty cycle (v out /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4628 f04 rms input ripple current dc load current 6-phase 4-phase 3-phase 2-phase 1-phase
ltm4628 15 4628fd a pplica t ions i n f or m a t ion figure 5. operating frequency vs f set pin voltage frequency selection and phase-locked loop (mode_pllin and f set pins) the ltm4628 device is operated over a range of frequencies to improve power conversion efficiency. it is recommended to operate the lower output voltages or lower duty cycle conversions at lower frequencies to improve efficiency by lowering power mosfet switching losses. higher output voltages or higher duty cycle conversions can be operated at higher frequencies to limit inductor ripple current. the efficiency graphs will show an operating frequency chosen for that condition. the ltm4628 switching frequency can be set with an external resistor from the f set pin to sgnd. an accurate 10a current source into the resistor will set a voltage that programs the frequency or a dc voltage can be applied. figure 5 shows a graph of frequency setting verses programming voltage. an external clock can be applied to the mode_pllin pin from 0 v to intv cc over a frequency range of 400 khz to 780 khz. the clock input high threshold is 1.6 v and the clock input low threshold is 0.5 v. the ltm4628 has the pll loop filter components on board. the frequency setting resistor should always be present to set the initial switching frequency before locking to an external clock . both regulators will operate in continuous mode while being externally clocked. the output of the pll phase detector has a pair of comple- mentary current sources that charge and discharge the internal filter network. when the external clock is applied the f set frequency resistor is disconnected with an internal switch, and the current sources control the frequency adjustment to lock to the incoming external clock. when no external clock is applied, then the internal switch is on, thus connecting the external f set frequency set resistor for free run operation. minimum on-time minimum on-time t on is the smallest time duration that the ltm4628 is capable of turning on the top mosfet on either channel. it is determined by internal timing delays, and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: v out v in ? freq > t on(min) if the duty cycle falls below what can be accommodated by the minimum on- time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the output ripple and current will increase. the minimum on- time can be increased by lowering the switching fre- quency. a good rule of thumb is to use an 110ns on- time. f set pin voltage (v) 0 frequency (khz) 900 800 600 400 100 200 700 500 300 0 2 4628 f05 2.5 1 1.5 0.5
ltm4628 16 4628fd a pplica t ions i n f or m a t ion output voltage tracking output voltage tracking can be programmed externally using the track pins. the output can be tracked up and down with another regulator. the master regulators output is divided down with an external resistor divider that is the same as the slave regulators feedback divider to implement coincident tracking. the ltm4628 uses an accurate 60.4 k resistor internally for the top feedback resistor for each channel. figure 6 shows an example of coincident tracking. equations: v out _ slave = 1 + 60.4k r ta ? ? ? ? ? ? ? v track v track is the track ramp applied to the slaves track pin. v track has a control range of 0 v to 0.6 v, or the internal reference voltage. when the masters output is divided down with the same resistor values used to set the slaves output, then the slave will coincident track with the master until it reaches its final value. the master will continue to its final value from the slaves regulation point. voltage tracking is disabled when v track is more than 0.6 v. r ta in figure 6 will be equal to the r fb for coincident tracking. figure 7 shows the coincident tracking waveforms. the track pin of the master can be controlled by a capaci- tor placed on the master regulator track pin to ground. a 1.3 a current source will charge the track pin up to the reference voltage and then proceed up to intv cc . after the 0.6 v ramp, the track pin will no longer be in con- trol, and the internal voltage reference will control output regulation from the feedback divider. foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. the track pins are pulled low figure 7. output coincident tracking waveform figure 6. example of output tracking application circuit time master output slave output output voltage 4628 f07 4628 f06 ltm4628 v in temp run1 run2 track1 track2 f set c8 470f 6.3v r fb 60.4k r2 10k c6 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 mode_pllin clkout intv cc extv cc pgood1 pgood intv cc sgnd gnd 1.5v master diffp diffn diffout 40.2k pgood slave 1.2v at 8a 1.5v at 8a c7 470f 6.3v c4 100f 6.3v r4 100k r tb 60.4k r1 10k d1 5.1v zener 5v to 16v intermediate bus r6 120k c ss 0.1f c1 22f 25v r ta 60.4k c2 22f 25v c3 22f 25v c10 4.7f r9 10k intv cc ramp time t softstart = (c ss /1.3a) ? 0.6v
ltm4628 17 4628fd a pplica t ions i n f or m a t ion when the run pin is below 1.2 v. the total soft-start time can be calculated as: t soft-start = c ss 1.3a ? ? ? ? ? ? ? 0.6v regardless of the mode selected by the mode_pllin pin, the regulator channels will always start in pulse-skipping mode up to track = 0.5 v. between track = 0.5 v and 0.54v, it will operate in forced continuous mode and revert to the selected mode once track > 0.54 v. in order to track with another channel once in steady state operation, the ltm4628 is forced into continuous mode operation as soon as v fb is below 0.54 v regardless of the setting on the mode_pllin pin. ratiometric tracking can be achieved by a few simple cal- culations and the slew rate value applied to the masters track pin. as mentioned above, the track pin has a control range from 0 to 0.6 v. the masters track pin slew rate is directly equal to the masters output slew rate in volts/time. the equation: mr sr ? 60.4k = r tb where mr is the masters output slew rate and sr is the slaves output slew rate in volts/time. when coincident tracking is desired, then mr and sr are equal, thus r tb is equal the 60.4k. r ta is derived from equation: r ta = 0.6v v fb 60.4k + v fb r fb ? v track r tb where v fb is the feedback voltage reference of the regula- tor, and v track is 0.6 v. since r tb is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then r ta is equal to r fb with v fb = v track . therefore r tb = 60.4 k, and r ta = 60.4 k in figure 6. in ratiometric tracking, a different slew rate maybe desired for the slave regulator. r tb can be solved for when sr is slower than mr. make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. for example, mr = 1.5v/1ms, and sr = 1.2v/1ms. then r tb = 76.8k. solve for r ta to equal to 49.9k. each of the track pins will have the 1.3 a current source on when a resistive divider is used to implement tracking on that specific channel. this will impose an offset on the track pin input. smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 60.4 k is used then a 6.04 k can be used to reduce the track pin offset to a negligible value. power good the pgood pins are open drain pins that can be used to monitor valid output voltage regulation. this pin monitors a 7.5% window around the regulation point. a resistor can be pulled up to a particular supply voltage no greater than 6v maximum for monitoring. stability compensation the module has already been internally compensated for all output voltages. table 4 is provided for most application requirements. ltpowercad is available for other control loop optimization. run enable the run pins have an enable threshold of 1.4 v maximum, typically 1.25 v with 150 mv of hysteresis. they control the turn-on of each of the channels. these pins can be pulled up to v in for 5 v operation, or a 5 v zener diode can be placed on the pins and a 10 k to 100 k resistor can be placed up to higher than 5v input for enabling the chan- nels. the run pins can also be used for output voltage sequencing. in parallel operation the run pins can be tie together and controlled from a single control. see the typical application circuits in figure 28. the run pin can also be left floating. the run pin has a 1 a pull- up cur- rent source that increases by an additional 4.5 a during ramp-up once above the on/off threshold.
ltm4628 18 4628fd a pplica t ions i n f or m a t ion intv cc and extv cc the ltm4628 module has an internal 5 v low dropout regulator that is derived from the input voltage. this regulator is used to power the control circuitry and the power mosfet drivers. this regulator can source up to 70ma, and typically uses ~30 ma for powering the device at the maximum frequency. extv cc allows an external 5 v supply to power the ltm4628 and reduce power dissipation from the internal low dropout 5v regulator. the power loss savings can be calculated by: ( v in C 5v) ? 30ma = p loss extv cc has a threshold of 4.7 v for activation, and a maxi- mum rating of 6 v. when using a 5 v input, connect this 5v input to extv cc also to maintain a 5 v gate drive level. v in has to be sequenced on before extv cc , and extv cc must be sequenced off before v in . differential remote sense amplifier an accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. this is especially true for high current loads. the amplifier can be used on one of the two channels, or on a single parallel output. it is very important that the diffp and diffn are connected properly at the output, and diffout is connected to either v outs1 or v outs2 . in parallel operation, the diffp and diffn are connected properly at the output, and diffout is connected to one of the v outs pins. review the parallel schematics in figure 31 and review figure 2. sw pins the sw pins are generally for testing purposes by moni- toring these pins. these pins can also be used to dampen out switch node ringing caused by lc parasitic in the switched current paths. usually a series r-c combina- tion is used, called a snubber circuit. the resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. if the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. the inductance is usually easier to predict. it combines the power path board inductance in combination with the mosfet interconnect bond wire inductance. first the sw pin can be monitored with a wide bandwidth scope with a high frequency scope probe. the ring fre- quency can be measured for its value. the impedance z can be calculated: z l = 2fl, where f is the resonant frequency of the ring, and l is the total parasitic inductance in the switch path. if a resistor is selected that is equal to z, then the ringing should be dampened. the snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. calculated by: z c = 1/(2fc). these values are a good place to start with. modification to these components should be made to attenuate the ringing with the least amount the power loss. temperature diode monitoring the ltm4628 has an on board 1 n4148 silicon diode at the temp pin that can be used to monitor temperature. the diode is mounted very close to internal power switches. the forward voltage of a silicon diode is temperature dependent based on the following equation: i d = i s ? e v d ? v t ? ? ? ? ? ? or v d = ? v t ? ln i d i s where i d is the diode current, v d is the diode voltage, is the ideality factor ( typically close to 1.0) and i s (satura- tion current) is a process dependent parameter. v t can be broken out to: v t = k ? t q where t is the diode junction temperature in kelvin, q is the electron charge and k is boltzmanns constant. v t is approximately 26 mv at room temperature (298 k) and scales linearly with kelvin temperature. it is this linear
ltm4628 19 4628fd a pplica t ions i n f or m a t ion figure 8. silicon diode voltage v d vs temperature figure 9. the 1n4148 diode voltage v d vs temperature temperature relationship that makes diodes suitable temperature sensors. the i s term in the equation above is the extrapolated current through a diode junction when the diode has zero volts across the terminals. the i s term varies from process to process, varies with temperature, and by definition must always be less than i d . combining all of the constants into one term: k d = ? k q where k d = 8.62 ?5 , and knowing ln(i d /i s ) is always posi- tive because i d is always greater than i s , leaves us with the equation that: v d = t(kelvin) ? k d ? ln i d i s where v d appears to increase with temperature. it is com- mon knowledge that a silicon diode biased with a current source has an approximate C2 mv/c temperature rela- tionship (figure 8), which is at odds with the equation. in fact, the i s term increases with temperature, reducing the ln(i d /i s ) absolute value yielding an approximate C2mv/c composite diode voltage slope. it is important that the bias current source be accurate and powered from a high impedance source. this is because the forward voltage drop is also a function of the current through the diode. the below equations show that when currents are a de- cade apart the v d difference is 60 mv; therefore the 10 a current source error will affect the diode forward voltage at temperature. kt/q = 26mv v d1 C v d2 = kt/q ln(i d1 )/(i d2 ) where v d1 C v d2 is the difference in the diode forward voltage with the i d1 and i d2 current difference. several 1 n4148 diodes were tested with 100 a of current and figure 9 shows the results. the 100 a current source provided the best repeatability for each diode. the tested diodes are very close to C2.2mv/ c to C2.4 mv/c slope while each are biased with 100 a through a 120k pull-up resistor to 12 v. the figure 9 graph can be used to calibrate and measure ltm4628 internal temperature by measuring the diode v d value. temperature (c) ?273 diode voltage (v d ) 1.4 1.2 1.0 0.6 0.8 0.2 0.4 0 27 127 4628 f08 227 i d = 10a ?73 ?173 temperature (c) ?100 1n4148 diode voltage (v d ) 0.8 0.7 0.6 0.5 0.3 0.1 0.2 0.4 0 50 100 150 4628 f09 200 0?50
ltm4628 20 4628fd a pplica t ions i n f or m a t ion thermal considerations and output current derating the thermal resistances reported in the pin configura- tion section of the data sheet are consistent with those parameters defined by jesd 51-12 and are intended for use with finite element analysis ( fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per- formed on a module package mounted to a hardware test board defined by jesd 51-9 ( test boards for area array surface mount package thermal measurements). the motivation for providing these thermal coefficients is found in jesd 51-12 ( guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the module regulators thermal performance in their ap- plication at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin con- figuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance per- taining to ones application-usage, and can be adapted to correlate thermal per formance to ones own application. the pin configuration section gives four thermal coeffi- cients explicitly defined in jesd 51-12; these coefficients are quoted or paraphrased below: 1 ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. this environment is sometimes referred to as still air although natural convection causes the air to move . this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. 2 jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module regulator, the bulk of the heat flows out the bottom of the pack- age, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. 3 jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part . as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4 jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resis- tance where almost all of the heat flows through the bottom of the module regulator and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd 51-9. a graphical representation of the aforementioned thermal resistances is given in figure 10; blue resistances are contained within the module regulator, whereas green resistances are external to the module package.
ltm4628 21 4628fd a pplica t ions i n f or m a t ion figure 10. graphical representation of jesd 51-12 thermal coefficients as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd 51-12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclusively through the top or exclusively through bot- tom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the packagegranted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within the ltm4628, be aware there are multiple power devices and components dissipating power, with a con- sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicity but also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the ltm4628 and the specified pcb with all of the cor- rect material coefficients along with accurate power loss source definitions ; (2) this model simulates a software- defined jedec environment consistent with jesd 51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values ; (3) the model and fea software is used to evaluate the ltm4628 with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulate conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. the outcome of this process and due diligence yields a set of derating curves provided in other sections of this data sheet. after these laboratory tests have been performed the jb and ba are summed together to correlate quite well with the ltm4628 model with no airflow or heat sinking in a properly de - fined chamber. this jb + ba value is shown in the pin configuration section and should accurately equal the ja value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. 4628 f10 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance
ltm4628 22 4628fd a pplica t ions i n f or m a t ion the 1.0 v and 3.3 v power loss curves in figures 11 and 12 can be used in coordination with the load current derating curves in figures 13 to 24 for calculating an approximate ja thermal resistance for the ltm 462 8 with various heat sinking and airfow conditions . the power loss curves are taken at room temperature , and are increased with mul - tiplicative factors according to the ambient temperature . the approximate factors are : 1.35 for 115 c and 1.4 for 120 c. the derating curves are plotted with v out 1 and v out 2 in parallel single output operation starting at 16 a and the ambient temperature at 40 c. the output volt - ages are 1.0 v, and 3.3 v. these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance . thermal models are derived from several temperature measurements in a controlled tem - perature chamber along with thermal modeling analysis . the junction temperatures are monitored while ambi - ent temperature is increased with and without airfow . the power loss increase with ambient temperature change is factored into the derating curves . the junctions are maintained at 115 c to 120 c maximum while lowering output current or power with increasing ambient tem - perature . the decreased output current will decrease the internal m odule l oss as ambient temperature is increased . the monitored junction temperature of 120 c minus the ambient operating temperature specifes how much temperature rise can be allowed . as an example , in figure 14 the load current is derated to ~12 a at ~80 c with no air or heat sink and the power loss for the 12 v to 1.0 v at 12 a output is about 3.65 w. the 3.65 w loss is calculated with the ~2.7 w room temperature loss from the 12 v to 1.0 v power loss curve at 12 a, and the 1.35 multiplying factor at 120 c junction . if the 80 c ambient tempera - ture is subtracted from the 120 c junction temperature , then the difference of 40 c divided by 3.65 w equals a 10.9 c/w ja thermal resistance . table 2 specifes a 9.5 c/w to 10 c/w value which is very close. table 2 and table 3 provide equivalent thermal resistances for 1.0 v and 3.3 v outputs with and without airfow and heat sinking . the derived thermal resistances in tables 2 and 3 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient , thus maximum junction temperature . the no - airfow ja values have some variation from 9.5 c/w to 11 c /w depending on the 115 c to 120 c holding junction temperature . all other airfow thermal resistance values are more accurate . room temperature power loss can be derived from the effciency curves in the typical performance characteristics section and ad- justed with the above ambient temperature multiplicative factors . the printed circuit board is a 1.6 mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers . the pcb dimensions are 95 mm 76 mm . the bga heat sinks are listed in table 3.
ltm4628 23 4628fd a pplica t ions i n f or m a t ion figure 11. 1v power loss figure 12. 3.3v power loss figure 13. 5v to 1v derating curves, no heat sink figure 14. 12v to 1v derating curves, no heat sink output current (a) 0 power loss (w) 2 3 4 16 4628 f11 1 0 2 4 6 8 10 12 14 6 5 24v to 1v 12v to 1v 5v to 1v output current (a) 0 power loss (w) 4 5 6 16 4628 f12 3 2 0 4 8 12 14 2 6 10 1 8 7 24v to 3.3v power loss 12v to 3.3v power loss 5v to 3.3v power loss ambient temperature (c) 0 ch1 and ch2 cmbined load current 8 10 12 120 4628 f14 6 4 0 20 40 60 80 100 2 16 14 0 lfm 200 lfm 400 lfm ambient temperature (c) 0 ch1 and ch2 combined load current 8 10 12 120 4628 f13 6 4 0 40 80 100 20 60 2 16 14 0 lfm 200 lfm 400 lfm figure 15. 24v to 1v derating curves, no heat sink figure 16. 5v to 1v derating curves, with bga heat sink ambient temperature (c) 0 ch1 and ch2 combined load current 8 10 12 120 4628 f15 6 4 0 20 40 60 80 100 2 16 14 0 lfm 200 lfm 400 lfm ambient temperature (c) 0 ch1 and ch2 combined load current 8 10 12 120 4628 f16 6 4 0 20 40 60 80 100 2 16 14 0 lfm 200 lfm 400 lfm figure 17. 12 v to 1 v derating with bga heat sink figure 18. 24v to 1v derating curves with bga heat sink ambient temperature (c) 0 ch1 and ch2 combined load current 8 10 12 120 4628 f17 6 4 0 20 40 60 80 100 2 16 14 0 lfm 200 lfm 400 lfm ambient temperature (c) 0 ch1 and ch2 combined load current 8 10 12 120 4628 f18 6 4 0 20 40 60 80 100 2 16 14 0 lfm 200 lfm 400 lfm figure 19. 5v to 3.3v derating curves, no heat sink ambient temperature (c) 0 ch1 and ch2 combined load current 8 10 12 120 4628 f19 6 4 0 20 40 60 80 100 2 16 14 0 lfm 200 lfm 400 lfm
ltm4628 24 4628fd a pplica t ions i n f or m a t ion figure 20. 12v to 3.3v derating curves, no heat sink ambient temperature (c) 0 ch1 and ch2 combined load current 8 10 12 120 4628 f20 6 4 0 20 40 60 80 100 2 16 14 0 lfm 200 lfm 400 lfm figure 21. 24v to 3.3v derating curves, no heat sink figure 22. 5v to 3.3v derating curves with heat sink figure 23. 12v to 3.3v derating curves, with heat sink figure 24. 24v to 3.3v derating curves with heat sink ambient temperature (c) 0 ch1 and ch2 combined load current 8 10 12 120 4628 f21 6 4 0 20 40 60 80 100 2 16 14 0 lfm 200 lfm 400 lfm ambient temperature (c) 0 ch1 and ch2 combined load current 8 10 12 120 4628 f22 6 4 0 20 40 60 80 100 2 16 14 0 lfm 200 lfm 400 lfm ambient temperature (c) 0 ch1 and ch2 combined load current 8 10 12 120 4628 f23 6 4 0 20 40 60 80 100 2 16 14 0 lfm 200 lfm 400 lfm ambient temperature (c) 0 ch1 and ch2 combined load current 8 10 12 120 4628 f24 6 4 0 20 40 60 80 100 2 16 14 0 lfm 200 lfm 400 lfm
ltm4628 25 4628fd a pplica t ions i n f or m a t ion table 2. 1.0v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 13, 14, 15 5, 12, 24 figure 11 0 none 9.5 to 11 figures 13, 14, 15 5, 12, 24 figure 11 200 none 6.4 figures 13, 14, 15 5, 12, 24 figure 11 400 none 5.6 figures 16, 17, 18 5, 12, 24 figure 11 0 bga heat sink 9.0 to 10.5 figures 16, 17, 18 5, 12, 24 figure 11 200 bga heat sink 6.5 figures 16, 17, 18 5, 12, 24 figure 11 400 bga heat sink 4.8 table 3. 3.3v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 19, 20, 21 5, 12, 24 figure 12 0 none 9.5 to 11 figures 19, 20, 21 5, 12, 24 figure 12 200 none 6.75 figures 19, 20, 21 5, 12, 24 figure 12 400 none 6.4 figures 22, 23, 24 5, 12, 24 figure 12 0 bga heat sink 9.0 to 10.5 figures 22, 23, 24 5, 12, 24 figure 12 200 bga heat sink 6.3 figures 22, 23, 24 5, 12, 24 figure 12 400 bga heat sink 4.8 heat sink manufacturer part number website aavid thermalloy 375424b00034g www.aavid.com
ltm4628 26 4628fd table 4 output voltage response vs component matrix (refer to figure 28) 0a to 4a load step typical measured values c out1 and c out2 ceramic vendors value part number c out1 and c out2 bulk vendors value part number c in (bulk) part number vendors avx 10f 35v 1812dd106 kat sanyo poscap 470f 2r5 2r5tpd470m5 47f 35v 35svpd47m sanyo oscon murata 22f 16v grm43er61c226ke01 sanyo poscap 470f 6.3v 6tpd470m tdk 100f 6.3v c4532x5r0j107mz murata 100f 6.3v grm32er60j107m avx 100f 6.3v 18126d107 mat v out (v) c in (ceramic) c in (bulk)* c out1 (ceramic) c out2 (bulk) c ff (pf) v in (v) droop (mv) p-p deviation (mv) recovery time (s) load step (a/s) r fb (k) freq. (khz) 1 22f 3 47f 100f 470f 5,12 60 120 30 4 90.9 400 1 22f 3 47f 100f 4 47 5,12 50 100 20 4 90.9 400 1.2 22f 3 47f 100f 470f 5,12 60 120 30 4 60.4 500 1.2 22f 3 47f 100f 4 47 5,12 55 110 20 4 60.4 500 1.5 22f 3 47f 100f 470f 5,12 60 120 30 4 40.2 500 1.5 22f 3 47f 100f 4 47 5,12 66 120 20 4 40.2 500 1.8 22f 3 47f 100f 470f 5,12 60 120 30 4 30.1 500 1.8 22f 3 47f 100f 4 47 5,12 65 130 20 4 30.1 500 2.5 22f 3 47f 100f 4 47 5,12 70 140 30 4 19.1 500 2.5 22f 3 47f 100f 470f 5,12 70 140 30 4 19.1 500 3.3 22f 3 47f 100f 470f 5,12 80 160 30 4 13.3 700 3.3 22f 3 47f 100f 47 5,12 100 200 30 4 13.3 700 5 22f 3 47f 100f 220f 47 12 125 200 30 4 8.25 750 * bulk capacitance is optional if v in has very low input impedance. a pplica t ions i n f or m a t ion
ltm4628 27 4628fd a pplica t ions i n f or m a t ion figures 25 and 26 show thermal images of the ltm4628 in lga package with or without bga heat sink and no air flow or 200lfm air flow. figure 25a.12v in to 3.3v out , 16a, no heat sink, no air flow figure 25b.12v in to 3.3v out , 16a, no heat sink, 200lfm these images equate to a paralleled 3.3 v output at 16a design operating at 92% efficiency from 12v input. figure 26a. 12v in to 3.3v out ,16a, with heat sink, no air flow figure 26b. 12v in to 3.3v out ,16a, with heat sink, 200lfm figure 25 figure 26
ltm4628 28 4628fd safety considerations the ltm4628 modules do not provide galvanic isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the device does support thermal shutdown and over current protection. a temperature diode is provided for monitoring internal temperature. layout checklist/example the high integration of ltm4628 makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout consid- erations are still necessary. ? use large pcb copper areas for high current paths, including v in , gnd, v out1 and v out2 . it helps to mini- mize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci- tors next to the v in , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put via directly on the pad, unless they are capped or plated over. ? use a separated sgnd ground copper area for com- ponents connected to signal pins. connect the sgnd to gnd underneath the unit. ? for parallel modules, tie the v out , v fb , and comp pins together. use an internal layer to closely connect these pins together. the track pin can be tied a common capacitor for regulator soft-start. ? bring out test points on the signal pins for monitoring. figure 27 gives a good example of the recommended layout. lga and bga pcb layouts are identical with the exception of circle pads for bga ( see package description). a pplica t ions i n f or m a t ion figure 27. recommended pcb layout (lga shown, for bga use circle pads) gnd gnd gnd sgnd cntrl cntrl v out1 c out1 c out2 v out2 v in c in1 c in2 1 2 3 4 5 6 7 8 109 11 12 l k j h g f e d c b m a 4628 f27
ltm4628 29 4628fd figure 28. 7v in to 16v in , 1.5v and 1.2v outputs typical a pplica t ions 4628 f28 ltm4628 v in temp run1 run2 track1 track2 f set c out2 470f 6.3v r8 60.4k r2 10k c out1 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 mode_pllin clkout intv cc extv cc pgood1 pgood1 intv cc sgnd gnd track1 track2 diffp diffn diffout r6 40.2k pgood2 1.2v at 8a c7 470f 6.3v c4 100f 6.3v r4 100k r1 10k d1 5.1v zener 7v to 16v intermediate bus r6 120k c5 0.1f c9 0.1f c in3 22f 25v c in2 22f 25v c in1 22f 25v c10 4.7f 1.5v at 8a 10k c ff 100pf 1.2v intv cc figure 29. tw o phases, 1.5v at 16a design 4628 f29 ltm4628 v in temp run1 run2 track1 track1 track2 f set c8 470f 6.3v r5 40.2k r2 5k c6 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 pgood1 mode_pllin clkout intv cc extv cc pgood1 pgood1 1.5v at 16a intv cc sgnd gnd diffp diffn diffout c7 470f 6.3v c4 100f 6.3v r4 100k r1 10k d1 5.1v zener 7v to 16v intermediate bus r6 120k c9 0.1f c1 22f 25v c2 22f 25v c11 22f 25v c3 22f 25v c10 4.7f + +
ltm4628 30 4628fd typical a pplica t ions figure 30. 1.2v and 1v output tracking 4628 f30 ltm4628 v in temp run1 run2 track1 track2 f set c8 470f 6.3v r8 90.9k r2 10k c6 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 mode_pllin clkout intv cc extv cc pgood1 pgood1 intv cc sgnd gnd 1.2v diffp diffn diffout r5 60.4k pgood2 1v at 8a 1.2v at 8a c7 470f 6.3v c4 100f 6.3v r4 100k r9 60.4k r1 10k d1 5.1v zener 5v to 16v intermediate bus r6 120k c5 0.1f c1 22f 25v r7 90.9k c2 22f 25v c3 22f 25v c10 4.7f + + 10k intv cc
ltm4628 31 4628fd t ypical applica t ions figure 31. 4-phase, 1.2v at 32a 4628 f31 ltm4628 v in temp run1 run run1 run2 track1 track1 track2 f set c8 470f 6.3v r5 60.4k 1.2v at 32a r2 5k c6 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 comp v outs2 v out2 sw2 pgood2 pgood1 mode_pllin clkout clk1 clk1 intv cc extv cc pgood1 pgood1 intv cc sgnd gnd diffp diffn diffout c7 470f 6.3v c4 100f 6.3v r4 100k r1 10k d1 5.1v zener 7v to 16v intermediate bus r6 10k c1 22f 25v c2 22f 25v c3 22f 25v c10 4.7f + + ltm4628 v in temp run1 run2 track1 track2 f set c14 470f 6.3v c13 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 v fb comp comp2 v outs2 v out2 sw2 pgood2 pgood1 mode_pllin clkout intv cc extv cc pgood1 pgood1 sgnd gnd diffp diffn diffout c18 470f 6.3v c17 100f 6.3v r10 100k 7v to 16v intermediate bus r9 10k c5 22f 25v c19 0.22f c15 22f 25v c12 22f 25v c16 4.7f + + intvcc track1 v fb
ltm4628 32 4628fd table 5. ltm4628 component pinout package d escrip t ion pin id function pin id function pin id function pin id function pin id function pin id function a1 vout1 b1 vout1 c1 vout1 d1 gnd e1 gnd f1 gnd a2 vout1 b2 vout1 c2 vout1 d2 gnd e2 gnd f2 gnd a3 vout1 b3 vout1 c3 vout1 d3 gnd e3 gnd f3 gnd a4 vout1 b4 vout1 c4 vout1 d4 gnd e4 gnd f4 mode_pllin a5 vout1 b5 vout1 c5 vout1s d5 vfb1 e5 track1 f5 run1 a6 gnd b6 gnd c6 f set d6 sgnd e6 comp1 f6 sgnd a7 gnd b7 gnd c7 sgnd d7 vfb2 e7 comp2 f7 sgnd a8 vout2 b8 vout2 c8 vout2s d8 track2 e8 diffp f8 diffout a9 vout2 b9 vout2 c9 vout2 d9 gnd e9 diffn f9 run2 a10 vout2 b10 vout2 c10 vout2 d10 gnd e10 gnd f10 gnd a11 vout2 b11 vout2 c11 vout2 d11 gnd e11 gnd f11 gnd a12 vout2 b12 vout2 c12 vout2 d12 gnd e12 gnd f12 gnd pin id function pin id function pin id function pin id function pin id function pin id function g1 gnd h1 gnd j1 gnd k1 gnd l1 gnd m1 gnd g2 sw1 h2 gnd j2 vin k2 vin l2 vin m2 vin g3 gnd h3 gnd j3 vin k3 vin l3 vin m3 vin g4 phasmd h4 gnd j4 vin k4 vin l4 vin m4 vin g5 clkout h5 gnd j5 gnd k5 gnd l5 vin m5 vin g 6 sgnd h 6 gnd j6 temp k6 gnd l6 vin m6 vin g7 sgnd h7 gnd j7 extvcc k7 gnd l7 vin m7 vin g8 pgood2 h8 intvcc j8 gnd k8 gnd l8 vin m8 vin g9 pgood1 h9 gnd j9 vin k9 vin l9 vin m9 vin g10 gnd h10 gnd j10 vin k10 vin l10 vin m10 vin g11 sw2 h11 gnd j11 vin k11 vin l11 vin m11 vin g12 gnd h12 gnd j12 gnd k12 gnd l12 gnd m12 gnd p ackage p ho t os 15mm 15mm 4.32mm 15mm 4.92mm 15mm lga bga
ltm4628 33 4628fd p ackage descrip t ion lga package 144-lead (15mm 15mm 4.32mm) (reference ltc dwg # 05-08-1843 rev ?) please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 144 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature symbol aaa bbb eee tolerance 0.15 0.10 0.05 4.22 ? 4.42 detail b detail b substrate mold cap 0.27 ? 0.37 3.95 ? 4.05 bbb z z 15 bsc package top view 15 bsc 4 pad 1 corner x y aaa z aaa z detail a 13.97 bsc 1.27 bsc 13.97 bsc 0.12 ? 0.28 package bottom view 3 pads see notes suggested pcb layout top view 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 lga 144 0709 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? dia 0.630 pad 1 3x, c (0.22 x45) detail a 0.630 0.025 sq. 143x s yxeee l k j h g f e d c b m a 12345678 10 9 1112 lga package 144-lead (15mm 15mm 4.32mm) (reference ltc dwg # 05-08-1843 rev ?)
ltm4628 34 4628fd p ackage descrip t ion bga package 144-lead (15mm 15mm 4.92mm) (reference ltc dwg # 05-08-1921 rev ?) please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view pin 1 3 see notes suggested pcb layout top view bga 144 0312 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? detail a 0.0000 0.0000 detail a ?b (144 places) d a detail b package side view z m x yzddd m zeee 0.630 0.025 ? 144x e b e e b a2 f g bga package 144-lead (15mm 15mm 4.92mm) (reference ltc dwg # 05-08-1921 rev ?) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 detail b substrate a1 b1 ccc z mold cap symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.72 0.50 4.22 0.60 0.60 0.27 3.95 nom 4.92 0.60 4.32 0.75 0.63 15.00 15.00 1.27 13.97 13.97 0.32 4.00 max 5.12 0.70 4.42 0.90 0.66 0.37 4.05 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 144 // bbb z z h2 h1 0.0 f g h m l j k e a b c d 2 1 4 3 567 12 891011
ltm4628 35 4628fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 06/11 updated typical application efficiency graph updated pin configuration updated electrical characteristics updated pin functions section updated decoupling requirements table updated figure 3 various text updated in applications information section updated figures 29 and 31 1 2 3, 4 7, 8 9 13 11 to 22 30, 32 b 7/11 changed typical value of r fbhi1 , r fbhi2 to 60.4k updated decoupling requirements table 3 9 c 8/12 updated pin configuration to add the bga package. added v d1 C v d2 formula. 2 19 d 11/12 updated the pin configuration section. 2
ltm4628 36 4628fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 1112 rev d ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltm4619 dual 26v in , 4a dc/dc module regulator 4.5v v in 26.5v; 0.8v v out 5v ltm4615 triple low v in , 4a dc/dc module regulator 2.375 v in 5.5v; tw o 4a and one 1.5a output ltm4616 dual 8a, low v in , dc/dc module regulator 2.7v v in 5.5v; 0.6v v out 5v ltm4614 dual 4a, low v in , dc/dc module regulator 2.375v v in 5.5v; 0.8v v out 5v ltm4627 15a dc/dc module regulator 4.5v v in 20v; 0.6v v out 5v figure 32. 24v in , 5v and 3.3v outputs 4628 f32 ltm4628 v in temp run1 run2 track1 track2 f set c out2 470f 6.3v r8 13.3k r2 10k c out1 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 mode_pllin clkout intv cc extv cc pgood1 pgood1 5v sgnd gnd track1 track2 diffp diffn diffout r6 8.25k pgood2 3.3v at 8a c7 470f 6.3v c4 100f 6.3v r1 10k d1 5.1v zener 24v r6 240k c5 0.1f c9 0.1f c1 10f 35v c2 10f 35v c3 10f 35v c8 10f 35v c10 4.7f 5v at 8a 10k 3.3v intv cc

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